Typically, a semiconductor integrated circuit (IC) device incorporates a test mode enable circuit for generating a test mode enable signal. The test mode enable signal puts the IC device in a test mode for testing functional circuits in the IC device.
For example, a test mode enable circuit 101 disclosed in JP-H5-34409A is a 4-bit binary counter and has one input 102, as shown in FIG. 6. The test mode enable circuit 101 counts each pulse of a control signal fed to the input 102 and generates four test mode enable signals T1-T4, each of which corresponds to a different test mode. All of the test mode enable signals T1-T4 are reset to a low level, when a reset signal R (e.g., power-on reset signal) of the low level is fed to the test mode enable circuit 101.
An advantage of the test mode enable circuit 101 is that the four test mode enable signals T1-T4 are generated with only one input 102. However, the IC device may be accidentally put in the test mode by a noise signal applied to the input 102. The IC device can leave the test mode by resetting the reset signal R to the low level. However, if the reset signal R is the power-on reset signal and shared with other circuit blocks on the IC device, the IC device needs to be tuned off to leave the test mode. Therefore, not only the test mode enable circuit 101, but also the other circuit blocks are turned off.